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TTTC's Electronic Broadcasting Service |
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IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems
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SUBMISSION DEADLINE EXTENDED TO MAY 18, 2018
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CALL FOR PAPERS
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DFT is an annual Symposium providing an open forum for presentations in the field of defect and fault tolerance in VLSI and nanotechnology systems inclusive of emerging technologies. One of the unique features of this symposium is to combine new academic research with state-of-the-art industrial data, necessary ingredients for significant advances in this field. All aspects of design, manufacturing, test, reliability, and availability that are affected by defects during manufacturing and by faults during system operation are of interest. The topics include (but are not limited to) the following ones: 1. YIELD ANALYSIS AND MODELING: Defect/fault analysis and models; statistical yield modeling; diagnosis; critical area and other metrics. 2. TESTING TECHNIQUES: Built-in self-test; delay fault modeling and diagnosis; testing for analog and mixed circuits; online testing; signal and clock integrity. 3. DESIGN FOR TESTABILITY IN IC DESIGN: FPGA, SoC, NoC, ASIC, low power design and microprocessors. 4. ERROR DETECTION, CORRECTION, AND RECOVERY: Self-testing and self-checking solutions; error-control coding; fault masking and avoidance; recovery schemes, space/time redundancy; hw/sw techniques; architectural-specific techniques, system-level design-time or runtime strategies. 5. DEPENDABILITY ANALYSIS AND VALIDATION: Fault injection techniques and frameworks; dependability and characterization. 6. REPAIR, RESTRUCTURING AND RECONFIGURATION: Repairable logic; reconfigurable circuit design; DFT for on-line operation; self-healing; reliable FPGA-based systems. 7. DEFECT AND FAULT TOLERANCE: Reliable circuit/system synthesis; radiation hardened and/or tolerant processes and design; design space exploration for dependable systems, transient/soft faults and errors. 8. AGING AND LIFETIME RELIABILITY: Aging characterization and modeling; design and run-time reliability, thermal, and variability management and recovery. 9. DEPENDABLE APPLICATIONS AND CASE STUDIES: Methodologies and case study applications to Internet of Things, automotive, railway, avionics and space, autonomous systems, industrial control, etc. 10.EMERGING TECHNOLOGIES: Techniques for 2.5D/3D ICs, quantum computing architectures, memristors, spintronics, microfluidics, etc. 11.DESIGN FOR SECURITY: Fault attacks, fault tolerance-based countermeasures, scan-based attacks and counter-measures, hardware trojans, security vs. reliability trade-offs, interaction between VLSI test, trust, and reliability. |
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Prospective authors are invited to submit original and unpublished contributions. Two types of submissions are possible: (i) regular papers (6 pages), and (ii) short papers (4 pages). Both types will be included in the symposium proceedings and should adhere to the IEEE conference template, 2-columns style (available on conference web site), and submitted as a PDF file, electronically. Please refer to the symposium web page for updated information. Proposals for Special Sessions are also invited. For more information, visit symposium website and see the specific call. |
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Abstract submission deadline: May 4, 2018 Full paper submission deadline: May 18, 2018 Acceptance notification: July 6, 2018 Camera ready deadline: July 27, 2018 |
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| Additional Information | |
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Paper Publication: Proceedings will be published by the IEEE Computer Society and will appear in the Digital Library. All papers will be considered for the DFT 2018 Best Paper Award. Furthermore, selected papers will be considered for a special issue/section of an archival journal. Venue: The symposium is going back to North America on its 31st edition and will take place in the USA at the Wyndam Grant Hotel, Chicago Waterfront, on the south end of the Magnificent mile, on Chicago river. The Chicago metropolitan area has nearly 10 million people and is the third-largest in the United States. Chicago has often been called a global architecture capital and is considered one of the most important business centers in the world. |
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| Committee | |
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Organizing Committee General co-chairs:
Program co-chairs:
Publicity chair:
Publication chair:
Industrial liaison chair:
Program Committee
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| For more information, visit us on the web at: http://www.dfts.org/ |
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The CONFERENCE is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC). |
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IEEE
Computer Society-Test Technology Technical Council |
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TTTC CHAIR
PAST CHAIR
TTTC 1ST VICE CHAIR
SECRETARY TEST WEEK COORDINATOR TUTORIALS AND EDUCATION STANDARDS EUROPE MIDDLE EAST & AFRICA STANDING COMMITTEES ELECTRONIC MEDIA |
PRESIDENT OF BOARD SENIOR PAST CHAIR TTTC 2ND VICE CHAIR FINANCE TECHNICAL MEETINGS TECHNICAL ACTIVITIES ASIA & PACIFIC LATIN AMERICA NORTH AMERICA COMMUNICATIONS INDUSTRY ADVISORY BOARD |
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